mirror of
https://github.com/YosysHQ/yosys
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77 lines
2 KiB
Verilog
77 lines
2 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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(* techmap_celltype = "$mul $__mul" *)
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module \$__MULMXN (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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localparam A_ADJWIDTH = A_WIDTH + (A_SIGNED ? 0 : 1);
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localparam B_ADJWIDTH = B_WIDTH + (B_SIGNED ? 0 : 1);
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generate
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if (A_SIGNED) begin: blkA
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wire signed [A_ADJWIDTH-1:0] Aext = $signed(A);
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end
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else begin: blkA
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wire [A_ADJWIDTH-1:0] Aext = A;
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end
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if (B_SIGNED) begin: blkB
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wire signed [B_ADJWIDTH-1:0] Bext = $signed(B);
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end
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else begin: blkB
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wire [B_ADJWIDTH-1:0] Bext = B;
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end
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if (A_WIDTH >= B_WIDTH) begin
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CC_MULT #(
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.A_WIDTH(A_ADJWIDTH),
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.B_WIDTH(B_ADJWIDTH),
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.P_WIDTH(Y_WIDTH),
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) _TECHMAP_REPLACE_ (
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.A(blkA.Aext),
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.B(blkB.Bext),
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.P(Y)
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);
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end
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else begin // swap A,B
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CC_MULT #(
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.A_WIDTH(B_ADJWIDTH),
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.B_WIDTH(A_ADJWIDTH),
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.P_WIDTH(Y_WIDTH),
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) _TECHMAP_REPLACE_ (
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.A(blkB.Bext),
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.B(blkA.Aext),
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.P(Y)
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);
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end
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endgenerate
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endmodule
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