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https://github.com/YosysHQ/yosys
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51 lines
1.1 KiB
Python
51 lines
1.1 KiB
Python
from pyosys import libyosys as ys
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# loading design
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design = ys.Design()
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ys.run_pass("read_verilog tests/simple/fiedler-cooley.v", design)
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ys.run_pass("hierarchy -check -auto-top", design)
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# top module inspection
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top_module = design.top_module()
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for id, wire in top_module.wires_.items():
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if not wire.port_input and not wire.port_output:
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continue
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description = "input" if wire.port_input else "output"
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description += " " + wire.name.str()
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if wire.width != 1:
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frm = wire.start_offset
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to = wire.start_offset + wire.width
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if wire.upto:
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to, frm = frm, to
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description += f" [{to}:{frm}]"
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print(description)
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# synth
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ys.run_pass("synth", design)
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# adding the enable line
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enable_line = top_module.addWire("\\enable")
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enable_line.port_input = True
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top_module.fixup_ports()
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# hooking the enable line to the internal dff cells
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for cell in top_module.cells_.values():
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if cell.type != "$_DFF_P_":
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continue
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cell.type = "$_DFFE_PP_"
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cell.setPort("\\E", ys.SigSpec(enable_line))
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# run check
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top_module.check()
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ys.run_pass("stat", design)
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# write outputs
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ys.run_pass("write_verilog out.v", design)
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ys.run_pass("synth_ice40 -json out.json", design)
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