mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-10 17:58:07 +00:00
37 lines
1,005 B
Python
37 lines
1,005 B
Python
from pyosys import libyosys as ys
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class AllEnablePass(ys.Pass):
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def __init__(self):
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super().__init__(
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"all_enable",
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"makes all _DFF_P_ registers require an enable signal"
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)
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def execute(self, args, design):
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ys.log_header(design, "Adding enable signals\n")
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ys.log_push()
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top_module = design.top_module()
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if "\\enable" not in top_module.wires_:
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enable_line = top_module.addWire("\\enable")
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enable_line.port_input = True
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top_module.fixup_ports()
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for cell in top_module.cells_.values():
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if cell.type != "$_DFF_P_":
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continue
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cell.type = "$_DFFE_PP_"
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cell.setPort("\\E", ys.SigSpec(enable_line))
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ys.log_pop()
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p = AllEnablePass() # register the pass
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# using the pass
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design = ys.Design()
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ys.run_pass("read_verilog tests/simple/fiedler-cooley.v", design)
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ys.run_pass("hierarchy -check -auto-top", design)
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ys.run_pass("synth", design)
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ys.run_pass("all_enable", design)
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ys.run_pass("write_verilog out.v", design)
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ys.run_pass("synth_ice40 -json out.json", design)
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