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yosys/backends/firrtl
Jim Lawson 93d19dc2fb Add support for module instances.
Don't pad logical operands to one bit.
Use operand width and signedness in $reduce_bool.
Shift amounts are unsigned and shouldn't be padded.
Group "is invalid" with the wire declaration, not its use (otherwise it is incorrectly wired to 0).
2018-08-23 14:35:11 -07:00
..
.gitignore Progress in FIRRTL back-end 2016-11-18 00:32:35 +01:00
firrtl.cc Add support for module instances. 2018-08-23 14:35:11 -07:00
Makefile.inc Added first draft of FIRRTL back-end 2016-11-17 23:36:47 +01:00
test.sh More progress on Firrtl backend. 2017-02-13 11:17:53 -08:00
test.v More progress on Firrtl backend. 2017-02-13 11:17:53 -08:00