Clifford Wolf 93a70959f3 Replaced RTLIL::Const::str with generic decoder method		2013-12-04 14:14:05 +01:00
..
abc	Tighter integration of ABC build	2013-11-27 09:08:35 +01:00
cmds	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
extract	Automatically run "proc" on extract map files	2013-07-24 20:19:08 +02:00
fsm	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
hierarchy	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
memory	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
opt	Cleanups and bugfixes in response to new internal cell checker	2013-11-11 00:39:45 +01:00
proc	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00
sat	Started implementing undef support in "sat" command	2013-11-25 21:40:00 +01:00
scc	fixed typos	2013-03-18 07:28:31 +01:00
submod	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
techmap	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00