mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-14 04:48:46 +00:00
46 lines
1.3 KiB
Plaintext
46 lines
1.3 KiB
Plaintext
# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
|
|
read_verilog ../common/memory_params.v
|
|
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
|
|
synth_xilinx -top sync_ram_sdp
|
|
cd sync_ram_sdp
|
|
select -assert-count 1 t:RAMB18E1
|
|
|
|
design -reset
|
|
read_verilog ../common/memory_params.v
|
|
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
|
|
synth_xilinx -top sync_ram_sdp
|
|
cd sync_ram_sdp
|
|
select -assert-count 1 t:RAMB18E1
|
|
|
|
design -reset
|
|
read_verilog ../common/memory_params.v
|
|
chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
|
|
synth_xilinx -top sync_ram_sdp
|
|
cd sync_ram_sdp
|
|
select -assert-count 1 t:RAMB18E1
|
|
|
|
design -reset
|
|
read_verilog ../common/memory_params.v
|
|
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
|
|
synth_xilinx -top sync_ram_sdp
|
|
cd sync_ram_sdp
|
|
select -assert-count 1 t:RAMB18E1
|
|
|
|
# Anything memory bits < 1024 -> LUTRAM
|
|
design -reset
|
|
read_verilog ../common/memory_params.v
|
|
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
|
|
synth_xilinx -top sync_ram_sdp
|
|
cd sync_ram_sdp
|
|
select -assert-count 0 t:RAMB18E1
|
|
select -assert-count 4 t:RAM128X1D
|
|
|
|
# More than 18K bits and addr <= 36: -> RAMB36E1
|
|
design -reset
|
|
read_verilog ../common/memory_params.v
|
|
chparam -set ADDRESS_WIDTH 15 -set DATA_WIDTH 1 sync_ram_sdp
|
|
synth_xilinx -top sync_ram_sdp
|
|
cd sync_ram_sdp
|
|
select -assert-count 1 t:RAMB36E1
|
|
|