3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 18:05:24 +00:00
yosys/backends/cxxrtl
whitequark 93288b8eae cxxrtl: run edge detectors only once in eval().
As a result, Minerva SRAM SoC runs ~15% faster.
2020-04-22 12:47:28 +00:00
..
cxxrtl.cc cxxrtl: run edge detectors only once in eval(). 2020-04-22 12:47:28 +00:00
cxxrtl.h cxxrtl: use one delta cycle for immediately converging netlists. 2020-04-21 16:14:45 +00:00
Makefile.inc write_cxxrtl: new backend. 2020-04-09 04:08:36 +00:00