Eddie Hung 9314a0a42e Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor		2019-08-28 10:51:39 -07:00
..
tests	Improved xilinx "bram1" test	2015-04-09 17:12:12 +02:00
.gitignore
abc_xc7.box
abc_xc7.lut
abc_xc7_nowide.lut
arith_map.v
brams_init.py
cells_map.v
cells_sim.v	Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor	2019-08-28 10:51:39 -07:00
cells_xtra.py	move attributes to wires	2019-08-13 19:36:59 +00:00
cells_xtra.v	move attributes to wires	2019-08-13 19:36:59 +00:00
ff_map.v
lut_map.v
lutrams.txt
lutrams_map.v
Makefile.inc
mux_map.v
synth_xilinx.cc	Merge branch 'master' into mwk/xilinx_bufgmap	2019-08-26 13:25:17 -07:00
xc6s_brams.txt
xc6s_brams_bb.v	move attributes to wires	2019-08-13 19:36:59 +00:00
xc6s_brams_map.v	RST -> RSTBRST for RAMB8BWER	2019-07-29 16:05:44 -07:00
xc7_brams.txt
xc7_brams_bb.v	move attributes to wires	2019-08-13 19:36:59 +00:00
xc7_brams_map.v