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yosys/techlibs/xilinx
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Marcelina Kościelnicka 347dd01c2f xilinx: Fix srl regression. 
Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9.  Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
2020-07-12 23:41:27 +02:00
..
tests
.gitignore
abc9_model.v abc9_ops: add -prep_bypass for auto bypass boxes; refactor 2020-05-14 10:33:56 -07:00
arith_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
brams_init.py
cells_map.v xilinx: Use dfflegalize. 2020-07-09 18:54:23 +02:00
cells_sim.v xilinx: tidy up cells_sim.v a little 2020-05-25 09:48:11 -07:00
cells_xtra.py xilinx: Mark IOBUFDS.IOB as external pad 2020-03-20 14:37:38 +01:00
cells_xtra.v xilinx: Mark IOBUFDS.IOB as external pad 2020-03-20 14:37:38 +01:00
ff_map.v xilinx: Use dfflegalize. 2020-07-09 18:54:23 +02:00
lut4_lutrams.txt
lut6_lutrams.txt
lut_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
lutrams_map.v
Makefile.inc xilinx: Use dfflegalize. 2020-07-09 18:54:23 +02:00
mux_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
synth_xilinx.cc xilinx: Fix srl regression. 2020-07-12 23:41:27 +02:00
xc2v_brams.txt
xc2v_brams_map.v
xc3s_mult_map.v
xc3sa_brams.txt
xc3sda_brams.txt
xc3sda_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_brams.txt
xc6s_brams_map.v
xc6s_dsp_map.v
xc7_brams_map.v
xc7_dsp_map.v
xc7_xcu_brams.txt
xcu_brams_map.v
xcu_dsp_map.v
xcup_urams.txt
xcup_urams_map.v
xilinx_dffopt.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00