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2025-10-27 01:39:23 +00:00
Code
Activity
92aaad706d
yosys
/
frontends
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Martin Povišer
92aaad706d
Merge
6f7f71fe03
into
012ddc2f1e
2025-09-08 10:10:29 +12:00
..
aiger
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
aiger2
aiger2: Clean debug print
2024-12-10 14:27:55 +01:00
ast
simplify: fix $initstate segfault
2025-08-12 12:39:36 +02:00
blif
Merge
6f7f71fe03
into
012ddc2f1e
2025-09-08 10:10:29 +12:00
json
fix handling of escaped chars in json backend and frontend
2022-02-18 17:13:09 +01:00
liberty
Liberty file caching with new
libcache
command
2025-04-03 13:39:35 +02:00
rpc
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
rtlil
read_rtlil: warn on assigns after switches in case rules
2024-11-21 22:41:13 +01:00
verific
verificsva: Fix typo in the cover only followed-by operator support
2025-08-04 15:38:19 +02:00
verilog
Fix handling of cases that look like sva labels again.
2025-09-05 11:54:13 +08:00