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yosys/tests/memories
Martin Povišer e82e5f8b13 rtlil: Adjust internal check for $mem_v2 cells
There's a mismatch between what `kernel/mem.cc` emits for memories
with no read ports and what the internal RTLIL check expects.

The point of dispute it whether some of the parameters relating to read
ports have a zero-width value in this case. The `mem.cc` code says no,
the internal checker says yes.

Surveying the other `$mem_v2` parameters, and internal cell parameters
in general, I am inclined to side with the `mem.cc` code.

This breaks RTLIL compatibility but for an obscure edge case.
2024-11-08 15:18:43 +01:00
..
.gitignore
amber23_sram_byte_en.v
firrtl_938.v
implicit_en.v
issue00335.v
issue00710.v
no_implicit_en.v Fixed bug in memory_share feedback-to-en code 2014-07-19 15:32:14 +02:00
nordports.ys rtlil: Adjust internal check for $mem_v2 cells 2024-11-08 15:18:43 +01:00
read_arst.v
read_two_mux.v
run-test.sh
shared_ports.v
simple_sram_byte_en.v
trans_addr_enable.v
trans_sdp.v
trans_sp.v
wide_all.v
wide_read_async.v
wide_read_mixed.v
wide_read_sync.v
wide_read_trans.v
wide_thru_priority.v
wide_write.v