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10 lines
276 B
Verilog
10 lines
276 B
Verilog
module test(a, y);
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`define MSB_LSB_SEP :
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`define get_msb(off, len) ((off)+(len)-1)
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`define get_lsb(off, len) (off)
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`define sel_bits(offset, len) `get_msb(offset, len) `MSB_LSB_SEP `get_lsb(offset, len)
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input [31:0] a;
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output [7:0] y;
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assign y = a[`sel_bits(16, 8)];
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endmodule
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