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https://github.com/YosysHQ/yosys
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62196cbc0a
- Add explicitly handling of A_WIDTH=1 for completeness - mux2 uses one LUT3 instead of a hard mux (which did use LUTs anyway) - mux4 uses one LUT4 instead of hard muxes (which did use LUTs anyway) - mux8 uses only bottom half of a slice - Add a mux12 for intermediate variant between mux8 and mux16 - For sizes larger than 16 inputs, instantiate the right mux size - More comments about implementation choices - More tests including with -widemux and -abc9, and more comments
82 lines
1.2 KiB
Verilog
82 lines
1.2 KiB
Verilog
module mux2 (S,A,B,Y);
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input S;
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input A,B;
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output reg Y;
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always @(*)
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Y = (S)? B : A;
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endmodule
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module mux4 ( S, D, Y );
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input[1:0] S;
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input[3:0] D;
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output Y;
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reg Y;
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wire[1:0] S;
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wire[3:0] D;
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always @*
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begin
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case( S )
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0 : Y = D[0];
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1 : Y = D[1];
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2 : Y = D[2];
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3 : Y = D[3];
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endcase
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end
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endmodule
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module mux8 ( S, D, Y );
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input[2:0] S;
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input[7:0] D;
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output Y;
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reg Y;
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wire[2:0] S;
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wire[7:0] D;
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always @*
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begin
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case( S )
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0 : Y = D[0];
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1 : Y = D[1];
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2 : Y = D[2];
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3 : Y = D[3];
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4 : Y = D[4];
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5 : Y = D[5];
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6 : Y = D[6];
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7 : Y = D[7];
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endcase
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end
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endmodule
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module mux12 (D, S, Y);
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input [11:0] D;
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input [3:0] S;
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output Y;
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wire[15:0] D16;
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assign D16 = {4'bx, D};
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assign Y = D16[S];
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endmodule
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module mux16 (D, S, Y);
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input [15:0] D;
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input [3:0] S;
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output Y;
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assign Y = D[S];
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endmodule
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module mux20 (D, S, Y);
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input [19:0] D;
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input [4:0] S;
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output Y;
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wire[31:0] D32;
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assign D32 = {12'bx, D};
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assign Y = D32[S];
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endmodule
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