mirror of
https://github.com/YosysHQ/yosys
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62 lines
1.3 KiB
Plaintext
62 lines
1.3 KiB
Plaintext
read_verilog <<EOF
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module gate(input signed [2:0] a1, input signed [2:0] b1,
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input [1:0] a2, input [3:0] b2, input c, input d, output signed [3:0] y);
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wire signed [3:0] ab1;
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assign ab1 = a1 * b1;
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assign y = ab1 + a2*b2 + c + d + 1;
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endmodule
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EOF
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prep
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equiv_opt -assert alumacc
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design -load postopt
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stat
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design -save save
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equiv_opt -assert maccmap
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design -load save
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equiv_opt -assert maccmap -unmap
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design -reset
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read_verilog <<EOF
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module gate(input signed [2:0] a1, input signed [1:0] b1, output signed [3:0] y);
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assign y = a1 * b1;
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endmodule
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EOF
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prep
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equiv_opt -assert alumacc
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design -load postopt
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stat
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design -save save
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equiv_opt -assert maccmap
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design -load save
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equiv_opt -assert maccmap -unmap
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design -reset
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read_verilog <<EOF
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module gate(input [2:0] a, input [1:0] b, output [3:0] y);
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assign y = a * b;
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endmodule
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EOF
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prep
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equiv_opt -assert alumacc
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design -load postopt
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stat
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design -save save
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equiv_opt -assert maccmap
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design -load save
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equiv_opt -assert maccmap -unmap
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design -reset
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read_verilog <<EOF
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module gate(input [2:0] a, input [1:0] b, input [1:0] c, output [3:0] y);
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assign y = a * b - c;
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endmodule
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EOF
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prep
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equiv_opt -assert alumacc
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design -load postopt
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stat
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design -save save
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equiv_opt -assert maccmap
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design -load save
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equiv_opt -assert maccmap -unmap
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