mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
0ec5f1b756
- Techlib pmgens are now in relevant techlibs/*. - `peepopt` pmgens are now in passes/opt. - `test_pmgen` is still in passes/pmgen. - Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location, as well as the `#include`s. - Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the top level Makefile. - Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir $@))`.
41 lines
2.2 KiB
Makefile
41 lines
2.2 KiB
Makefile
# ISC License
|
|
#
|
|
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
|
|
#
|
|
# Permission to use, copy, modify, and/or distribute this software for any
|
|
# purpose with or without fee is hereby granted, provided that the above
|
|
# copyright notice and this permission notice appear in all copies.
|
|
#
|
|
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
|
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
|
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
|
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
|
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
|
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|
|
|
|
|
|
|
OBJS += techlibs/microchip/synth_microchip.o
|
|
OBJS += techlibs/microchip/microchip_dffopt.o
|
|
|
|
$(eval $(call add_share_file,share/microchip,techlibs/microchip/arith_map.v))
|
|
$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_map.v))
|
|
$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_sim.v))
|
|
$(eval $(call add_share_file,share/microchip,techlibs/microchip/polarfire_dsp_map.v))
|
|
|
|
$(eval $(call add_share_file,share/microchip,techlibs/microchip/brams_defs.vh))
|
|
$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM_map.v))
|
|
$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM.txt))
|
|
$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM_map.v))
|
|
$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM.txt))
|
|
|
|
OBJS += techlibs/microchip/microchip_dsp.o
|
|
GENFILES += techlibs/microchip/microchip_dsp_pm.h
|
|
GENFILES += techlibs/microchip/microchip_dsp_CREG_pm.h
|
|
GENFILES += techlibs/microchip/microchip_dsp_cascade_pm.h
|
|
techlibs/microchip/microchip_dsp.o: techlibs/microchip/microchip_dsp_pm.h techlibs/microchip/microchip_dsp_CREG_pm.h techlibs/microchip/microchip_dsp_cascade_pm.h
|
|
$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_pm.h))
|
|
$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_CREG_pm.h))
|
|
$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_cascade_pm.h))
|