Marcelina Kościelnicka 90b89e5ebc Merge pull request #2232 from YosysHQ/mwk/gowin-sim-init ... gowin: Fix INIT values in sim library.		2020-07-05 12:02:31 +02:00
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.gitignore	gowin: Add missing .gitignore entries	2019-11-22 14:40:36 +01:00
arith_map.v	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
brams.txt	Harmonize BRAM/LUTRAM descriptions across all of Yosys.	2020-01-01 12:30:00 +00:00
brams_init.py	support bram initialisation	2019-09-05 17:25:51 +02:00
brams_init3.vh	GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow	2019-04-12 23:40:02 -05:00
brams_map.v	add 32-bit BRAM and byte-enables	2019-10-28 10:33:27 +01:00
cells_map.v	Update dff2dffe, dff2dffs, zinit to new FF types.	2020-06-23 18:24:53 +02:00
cells_sim.v	gowin: Fix INIT values in sim library.	2020-07-05 03:03:48 +02:00
lutrams.txt	Harmonize BRAM/LUTRAM descriptions across all of Yosys.	2020-01-01 12:30:00 +00:00
lutrams_map.v	Harmonize BRAM/LUTRAM descriptions across all of Yosys.	2020-01-01 12:30:00 +00:00
Makefile.inc	gowin: replace determine_init with setundef	2020-07-04 23:26:56 +02:00
synth_gowin.cc	gowin: replace determine_init with setundef	2020-07-04 23:26:56 +02:00