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https://github.com/YosysHQ/yosys
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62 lines
1.3 KiB
Verilog
62 lines
1.3 KiB
Verilog
`timescale 1 ns / 1 ps
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module testbench;
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reg clk, en, rst;
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wire [3:0] count;
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counter uut_counter(
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.clk(clk),
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.count(count),
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.en(en),
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.rst(rst)
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);
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initial begin
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clk <= 0;
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forever begin
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#50;
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clk <= ~clk;
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end
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end
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initial begin
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@(posedge clk);
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forever begin
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@(posedge clk);
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$display("%d", count);
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end
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end
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initial begin
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rst <= 1; en <= 0; @(posedge clk);
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rst <= 1; en <= 0; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 1; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 1; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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rst <= 0; en <= 1; @(posedge clk);
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rst <= 0; en <= 0; @(posedge clk);
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$finish;
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end
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endmodule
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