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21 lines
395 B
Verilog
21 lines
395 B
Verilog
module opt_share_test(
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input [15:0] a,
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input [15:0] b,
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input [15:0] c,
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input [1:0] sel,
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output reg [15:0] res
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);
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wire [15:0] add0_res = a+b;
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wire [15:0] add1_res = a+c;
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always @* begin
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case(sel)
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0: res = add0_res[10:0];
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1: res = add1_res[10:0];
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2: res = a - b;
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default: res = 32'bx;
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endcase
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end
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endmodule
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