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53 lines
1.5 KiB
Text
53 lines
1.5 KiB
Text
read_verilog -icells <<EOT
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module dlatch(input E, D, (* init = 8'hf0 *) output [7:0] Q);
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$_DLATCH_P_ ff0 (.E(E), .D(1'b0), .Q(Q[0]));
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$_DLATCH_N_ ff1 (.E(E), .D(1'b0), .Q(Q[1]));
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$_DLATCH_P_ ff2 (.E(E), .D(1'b1), .Q(Q[2]));
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$_DLATCH_N_ ff3 (.E(E), .D(1'b1), .Q(Q[3]));
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$_DLATCH_P_ ff4 (.E(E), .D(1'b0), .Q(Q[4]));
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$_DLATCH_N_ ff5 (.E(E), .D(1'b0), .Q(Q[5]));
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$_DLATCH_P_ ff6 (.E(E), .D(1'b1), .Q(Q[6]));
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$_DLATCH_N_ ff7 (.E(E), .D(1'b1), .Q(Q[7]));
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endmodule
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EOT
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design -save orig
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equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 01
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equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP?_ 0
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equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
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equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
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# Convert everything to ADFFs.
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design -load orig
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dfflegalize -cell $_DFF_PP0_ 01
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select -assert-count 12 t:$_NOT_
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select -assert-count 8 t:$_DFF_PP0_
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select -assert-none t:$_DFF_PP0_ t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflegalize -cell $_DFF_PP?_ 0
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select -assert-count 12 t:$_NOT_
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select -assert-count 4 t:$_DFF_PP0_
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select -assert-count 4 t:$_DFF_PP1_
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select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_NOT_ %% %n t:* %i
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# Convert everything to DFFSREs.
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design -load orig
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dfflegalize -cell $_DFFSRE_PPPP_ 0
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select -assert-count 12 t:$_NOT_
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select -assert-count 8 t:$_DFFSRE_PPPP_
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select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflegalize -cell $_DFFSRE_PPPP_ 1
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select -assert-count 12 t:$_NOT_
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select -assert-count 8 t:$_DFFSRE_PPPP_
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select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i
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