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5ea2c6e6e5
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
9 lines
98 B
Verilog
9 lines
98 B
Verilog
module simple_assign (
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input wire in,
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output wire out
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);
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assign out = in;
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endmodule
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