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yosys/tests/sim/assume_x_first_step.ys
Roland Coeurjoly 5ea2c6e6e5 Assume x values for missing signal data in FST 
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
2024-10-02 12:08:48 +02:00

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read_verilog simple_assign.v
sim -r simple_assign.vcd -scope simple_assign
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