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26 lines
301 B
Verilog
26 lines
301 B
Verilog
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module test01(a, b, y);
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input [3:0] a, b;
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output [3:0] y;
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assign temp1 = a + b;
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assign temp2 = ~temp1;
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assign y = temp2;
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endmodule
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// ------------------------------
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module test02(a, b, y);
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input [3:0] a, b;
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output [3:0] y;
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test01 test01_cell(A, B, Y);
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assign A = a, B = b, y = Y;
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endmodule
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