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yosys/tests/verilog/mem_bounds.ys
George Rennie 8fb3f88842 tests: remove -seq 1 from sat with -tempinduct where possible
* When used with -tempinduct mode, -seq <N> causes assertions to be
  ignored in the first N steps. While this has uses for reset modelling,
  for these test cases it is unnecessary and could lead to failures
  slipping through uncaught
2025-09-08 18:04:32 +02:00

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read_verilog -sv -mem2reg mem_bounds.sv
proc
flatten
opt -full
select -module top
async2sync
sat -verify -tempinduct -prove-asserts -show-all -enable_undef