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yosys/techlibs/xilinx
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Keith Rothman 1f9235ede5 Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-12 09:35:15 -07:00
..
tests
.gitignore
arith_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
brams.txt Added read-enable to memory model 2015-09-25 12:23:11 +02:00
brams_bb.v
brams_init.py Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
brams_map.v Revert BRAM WRITE_MODE changes. 2019-03-04 09:22:22 -08:00
cells_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
cells_sim.v Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 2019-04-12 09:35:15 -07:00
cells_xtra.sh Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 2019-04-12 09:35:15 -07:00
cells_xtra.v Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 2019-04-12 09:35:15 -07:00
drams.txt
drams_map.v
ff_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
lut_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
Makefile.inc Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
synth_xilinx.cc Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 2019-03-19 20:30:28 +01:00