mirror of
https://github.com/YosysHQ/yosys
synced 2026-01-20 01:03:21 +00:00
8f80f8f655
The regex was matching 'public wires' and other lines. Now use $ anchor to match only lines ending with 'wires' or 'ports'.
64 lines
1.7 KiB
Tcl
64 lines
1.7 KiB
Tcl
yosys -import
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proc read_stats { file } {
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set fid [open $file]
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set result [read $fid]
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close $fid
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set ports 0
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set nets 0
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foreach line [split $result "\n"] {
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# Match only lines ending with "wires" or "ports" (not "public wires", "wire bits", etc)
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if [regexp {([0-9]+)[ \t]+wires[ \t]*$} $line -> n] {
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set nets [expr $nets + $n]
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}
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if [regexp {([0-9]+)[ \t]+ports[ \t]*$} $line -> n] {
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set ports [expr $ports + $n]
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}
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}
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return [list $nets $ports]
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}
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proc assert_count { type actual expected } {
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if {$actual != $expected} {
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puts "Error, $type count: $actual vs $expected expected"
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exit 1
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}
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}
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read_verilog test_splitnets.v
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hierarchy -auto-top
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procs
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design -save "pre"
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splitnets -ports_only -top_only
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write_verilog -noexpr "ports_only_in_top.v"
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tee -o "ports_only_in_top.txt" stat
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foreach {nets ports} [read_stats "ports_only_in_top.txt"] {}
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assert_count "nets" $nets 26
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assert_count "ports" $ports 16
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design -load "pre"
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splitnets -ports_only
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write_verilog -noexpr "ports_only_in_all.v"
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tee -o "ports_only_in_all.txt" stat
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foreach {nets ports} [read_stats "ports_only_in_all.txt"] {}
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assert_count "nets" $nets 30
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assert_count "ports" $ports 20
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design -load "pre"
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splitnets -ports -top_only
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write_verilog -noexpr "ports_nets_in_top.v"
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tee -o "ports_nets_in_top.txt" stat
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foreach {nets ports} [read_stats "ports_nets_in_top.txt"] {}
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assert_count "nets" $nets 30
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assert_count "ports" $ports 16
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design -load "pre"
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splitnets -ports
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write_verilog -noexpr "ports_nets_in_all.v"
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tee -o "ports_nets_in_all.txt" stat
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foreach {nets ports} [read_stats "ports_nets_in_all.txt"] {}
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assert_count "nets" $nets 40
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assert_count "ports" $ports 20
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exit 0
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