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54 lines
1.3 KiB
Verilog
54 lines
1.3 KiB
Verilog
//-----------------------------------------------------
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// Design Name : serial_crc_ccitt
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// File Name : serial_crc.v
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// Function : CCITT Serial CRC
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module serial_crc_ccitt (
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clk ,
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reset ,
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enable ,
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init ,
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data_in ,
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crc_out
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);
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//-----------Input Ports---------------
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input clk ;
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input reset ;
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input enable ;
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input init ;
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input data_in ;
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//-----------Output Ports---------------
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output [15:0] crc_out;
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//------------Internal Variables--------
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reg [15:0] lfsr;
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//-------------Code Start-----------------
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assign crc_out = lfsr;
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// Logic to CRC Calculation
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always @ (posedge clk)
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if (reset) begin
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lfsr <= 16'hFFFF;
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end else if (enable) begin
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if (init) begin
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lfsr <= 16'hFFFF;
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end else begin
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lfsr[0] <= data_in ^ lfsr[15];
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lfsr[1] <= lfsr[0];
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lfsr[2] <= lfsr[1];
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lfsr[3] <= lfsr[2];
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lfsr[4] <= lfsr[3];
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lfsr[5] <= lfsr[4] ^ data_in ^ lfsr[15];
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lfsr[6] <= lfsr[5];
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lfsr[7] <= lfsr[6];
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lfsr[8] <= lfsr[7];
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lfsr[9] <= lfsr[8];
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lfsr[10] <= lfsr[9];
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lfsr[11] <= lfsr[10];
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lfsr[12] <= lfsr[11] ^ data_in ^ lfsr[15];
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lfsr[13] <= lfsr[12];
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lfsr[14] <= lfsr[13];
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lfsr[15] <= lfsr[14];
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end
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end
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endmodule
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