N. Engelhardt d5e2061687 Merge pull request #1811 from PeterCrozier/typedef_scope ... Support module/package/interface/block scope for typedef names.		2020-03-30 13:55:39 +02:00
..
aiger	tests/aiger: Add missing .gitignore	2020-02-15 19:52:21 +01:00
arch	fix argument order for macOS compatibility	2020-03-18 15:11:49 +01:00
asicworld
bram
errors
fsm
hana
liberty
lut
memfile	Added 'set -e' into tests/memfile/run-test.sh	2020-02-06 10:45:40 -03:00
memories
opt	Merge pull request #1576 from YosysHQ/eddie/opt_merge_init	2020-02-05 14:56:26 -08:00
opt_share
proc	proc_clean: fix order of switch insertion.	2019-08-19 16:44:23 +00:00
realmath
rpc	rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors	2020-03-06 15:29:01 +01:00
sat	Merge pull request #1638 from YosysHQ/eddie/fix1631	2020-02-05 19:31:18 +01:00
select	Do not warn on empty selection with prefixed arg_memb.	2020-03-23 17:50:11 +00:00
share
simple	Fix partsel expr bit width handling and add test case	2020-03-08 16:12:12 +01:00
simple_abc9	Update simple_abc9 tests	2020-02-27 10:17:29 -08:00
smv
sva
svinterfaces
svtypes	Support module/package/interface/block scope for typedef names.	2020-03-23 20:07:22 +00:00
techmap	techmap: Fix cell names with _TECHMAP_REPLACE_.*	2020-03-23 11:17:07 +01:00
tools
unit
various	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
vloghtb