Eddie Hung 08139aa53a xilinx_srl now copes with word-level flops $dff{,e}		2019-08-23 12:22:46 -07:00
..
tests
.gitignore
abc_xc7.box
abc_xc7.lut
abc_xc7_nowide.lut
arith_map.v
brams_init.py
cells_map.v	xilinx: Fix missing cell name underscore in cells_map.v	2019-07-25 08:19:07 +01:00
cells_sim.v	Forgot one	2019-08-23 11:23:50 -07:00
cells_xtra.sh
cells_xtra.v
ff_map.v
lut_map.v
lutrams.txt	Work in progress for renaming labels/options in synth_xilinx	2019-07-18 14:20:43 -07:00
lutrams_map.v	Work in progress for renaming labels/options in synth_xilinx	2019-07-18 14:20:43 -07:00
Makefile.inc	Update Makefile too	2019-07-18 14:51:55 -07:00
mux_map.v
synth_xilinx.cc	xilinx_srl now copes with word-level flops $dff{,e}	2019-08-23 12:22:46 -07:00
xc6s_brams.txt
xc6s_brams_bb.v
xc6s_brams_map.v	RST -> RSTBRST for RAMB8BWER	2019-07-29 16:05:44 -07:00
xc7_brams.txt
xc7_brams_bb.v
xc7_brams_map.v