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14 lines
225 B
Text
14 lines
225 B
Text
read_verilog <<EOT
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module alu(
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);
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wire [1:0] p1, p2;
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assign p1 = 2'bx1;
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assign p2[0] = 1'b1;
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endmodule
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EOT
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proc
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opt_clean
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dump
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select -assert-count 1 w:p1 a:unused_bits=1 %i
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select -assert-count 1 w:p2 a:unused_bits=1 %i
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