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8e53d2e0bf
Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input.
12 lines
268 B
Verilog
12 lines
268 B
Verilog
module top(...);
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input [3:0] a;
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output o1 = 4'b0000 > a;
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output o2 = 4'b0000 <= a;
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output o3 = 4'b1111 < a;
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output o4 = 4'b1111 >= a;
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output o5 = a < 4'b0000;
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output o6 = a >= 4'b0000;
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output o7 = a > 4'b1111;
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output o8 = a <= 4'b1111;
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endmodule
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