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yosys/techlibs/common
2024-02-08 00:05:15 +01:00
..
.gitignore
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
cellhelp.py
cells.lib
cmp2lcu.v
cmp2lut.v
cmp2softlogic.v techlibs: Add cmp2softlogic.v to common 2023-11-13 10:42:12 +01:00
dff2ff.v
gate2lut.v
gen_fine_ffs.py Add $aldff and $aldffe: flip-flops with async load. 2021-10-02 18:12:52 +02:00
Makefile.inc techlibs: Add cmp2softlogic.v to common 2023-11-13 10:42:12 +01:00
mul2dsp.v
pmux2mux.v
prep.cc Run future as part of prep 2023-09-13 11:32:36 +02:00
simcells.v Add $aldff and $aldffe: flip-flops with async load. 2021-10-02 18:12:52 +02:00
simlib.v Add new $check cell to represent assertions with a message. 2024-02-01 20:10:39 +01:00
smtmap.v Add smtmap.v describing the smt2 backend's behavior for undef bits 2022-10-20 15:48:18 +02:00
synth.cc synth: Tweak phrasing of -booth help 2024-02-08 00:05:15 +01:00
techmap.v Add bitwise $bweqx and $bwmux cells 2022-11-30 18:24:35 +01:00