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Code Activity
yosys/frontends/verilog
History
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
..
.gitignore
const2ast.cc
Makefile.inc
preproc.cc Add support for "yosys -E" 2018-01-07 16:36:13 +01:00
verilog_frontend.cc Bugfix in verilog_defaults argument parser 2017-12-24 17:21:37 +01:00
verilog_frontend.h Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
verilog_lexer.l Add Verilog "automatic" keyword (ignored in synthesis) 2017-11-23 08:51:38 +01:00
verilog_parser.y Add $allconst and $allseq cell types 2018-02-23 13:14:47 +01:00