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40 lines
595 B
Text
40 lines
595 B
Text
# https://github.com/YosysHQ/yosys/issues/5979
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read_verilog -sv << EOF
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module top (
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input wire [1:0] sel,
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input wire [3:0] a,
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input wire [3:0] b,
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output reg [3:0] y
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);
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always @* begin
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case (sel)
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2'b1x: y = a;
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2'b10: y = b;
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default: y = a;
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endcase
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end
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endmodule
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module gold (
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input wire [1:0] sel,
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input wire [3:0] a,
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input wire [3:0] b,
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output reg [3:0] y
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);
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always @* begin
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if (sel == 2'b10) y = b;
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else y = a;
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end
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endmodule
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EOF
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proc
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opt -full
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select -assert-count 1 top/o:y %ci* top/i:b %i
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equiv_make gold top equiv
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cd equiv
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equiv_simple
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equiv_status -assert
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