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https://github.com/YosysHQ/yosys
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50 lines
749 B
Text
50 lines
749 B
Text
read_rtlil << EOT
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module \top
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wire width 4 input 0 \A
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wire width 4 input 1 \C
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wire width 2 input 2 \S
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wire width 4 output 3 \Y
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cell $pmux $0
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parameter \WIDTH 4
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parameter \S_WIDTH 2
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connect \A \A
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connect \B { \C \A }
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connect \S \S
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connect \Y \Y
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end
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end
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EOT
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equiv_opt -assert opt_reduce
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opt_reduce
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select -assert-count 0 t:$pmux
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select -assert-count 1 t:$mux
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design -reset
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read_rtlil << EOT
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module \top
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wire width 4 input 0 \A
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wire width 2 input 1 \S
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wire width 4 output 2 \Y
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cell $pmux $0
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parameter \WIDTH 4
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parameter \S_WIDTH 2
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connect \A \A
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connect \B { \A \A }
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connect \S \S
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connect \Y \Y
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end
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end
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EOT
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equiv_opt -assert opt_reduce
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opt_reduce
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select -assert-count 0 t:$pmux
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select -assert-count 0 t:$mux
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