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37 lines
1.2 KiB
Text
37 lines
1.2 KiB
Text
read_verilog <<EOT
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module top ( input d0, d1, d2, d3, ce, sr, clk, output reg q0, q1, q2, q3 );
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always @(posedge clk)
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begin
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if (sr) begin
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q0 <= 1'b0;
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q1 <= 1'b1;
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end else begin
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q0 <= d0;
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q1 <= d1;
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end
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if (ce) begin
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if (sr) begin
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q2 <= 1'b0;
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q3 <= 1'b1;
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end else begin
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q2 <= d2;
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q3 <= d3;
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end
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end
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end
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endmodule
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EOT
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hierarchy -top top
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proc
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flatten
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equiv_opt -assert -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DFFE_PP_ x -ff $_SDFF_PP?_ x -ff $_SDFFCE_PP?P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -extra-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUTFF_SR
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select -assert-count 1 t:LUTFF_SS
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select -assert-count 1 t:LUTFF_ESR
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select -assert-count 1 t:LUTFF_ESS
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select -assert-none t:LUTFF_SR t:LUTFF_SS t:LUTFF_ESR t:LUTFF_ESS %% t:* %D
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