yosys/tests/sat/initval.ys at 8da4c1ad8262216c5204c735f5297da33fed01fa - mirrors/yosys - Libre-Chip.org

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Clifford Wolf 3b52121d32 now ignore init attributes on non-register wires in sat command

2014-07-05 11:18:38 +02:00

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 read_verilog -sv initval.v
 proc;;
 sat -seq 10 -prove-asserts