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yosys/techlibs/xilinx
2019-06-26 11:38:28 -07:00
..
tests
.gitignore
abc_xc7.box Cleanup abc_box_id 2019-06-26 11:23:57 -07:00
abc_xc7.lut
abc_xc7_nowide.lut Add _nowide variants of LUT libraries in -nowidelut flows 2019-06-26 10:23:29 -07:00
arith_map.v
brams.txt
brams_bb.v
brams_init.py
brams_map.v
cells_map.v This optimisation doesn't seem to work... 2019-06-25 09:21:46 -07:00
cells_sim.v Cleanup abc_box_id 2019-06-26 11:23:57 -07:00
cells_xtra.sh Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
cells_xtra.v Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
drams.txt Add RAM32X1D support 2019-06-24 16:16:50 -07:00
drams_map.v Add RAM32X1D support 2019-06-24 16:16:50 -07:00
ff_map.v
lut_map.v
Makefile.inc
mux_map.v Change synth_xilinx's -nomux to -minmuxf <int> 2019-06-24 10:04:01 -07:00
synth_xilinx.cc Do not call opt with -full before muxcover 2019-06-26 11:38:28 -07:00