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13 lines
310 B
Text
13 lines
310 B
Text
read_verilog <<EOT
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module sub(input a, b, c, output y);
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assign y = (a & b) | c;
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endmodule
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module top(input a, b, c, d, output y, z);
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assign z = (a ^ b) & d;
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sub s_i (.a(a), .b(b), .c(c), .y(y));
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endmodule
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EOT
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hierarchy -top top
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techmap
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abc_new -liberty ../liberty/normal.lib -liberty ../liberty/dff.lib
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