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21 lines
340 B
Text
21 lines
340 B
Text
read_verilog -sv <<EOT
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module top (
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input logic [1:0] in_2,
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output logic [1:0] out_1
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);
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always @* begin
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out_1 = 2'd0;
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case ('d1 & in_2)
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2'd0: out_1 = 2'd0;
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2'd1: out_1 = in_2;
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2'd2: out_1 = 2'd1;
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2'd3: out_1 = 2'd3;
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default: out_1 = 2'd0;
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endcase
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end
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endmodule
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EOT
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hierarchy -top top
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proc
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equiv_opt -assert synth
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