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52 lines
1.2 KiB
Text
52 lines
1.2 KiB
Text
read_verilog -noblackbox << EOF
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(* raise_error=7 *)
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module top();
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endmodule
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(* raise_error="help me" *)
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module other();
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endmodule
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(* raise_error *)
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module def();
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endmodule
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EOF
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select -assert-mod-count 3 =*
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design -stash read
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# raise_error with int exits with status
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design -load read
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bugpoint -yosys ../../yosys -command raise_error -expect-return 7
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select -assert-mod-count 1 =*
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select -assert-mod-count 1 top
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# raise_error with string prints message
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design -load read
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rename top abc
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bugpoint -yosys ../../yosys -command raise_error -grep "help me"
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select -assert-mod-count 1 =*
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select -assert-mod-count 1 other
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# raise_error with no value exits with 1
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design -load read
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rename def zzy
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bugpoint -yosys ../../yosys -command raise_error -expect-return 1
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select -assert-mod-count 1 =*
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select -assert-mod-count 1 zzy
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# raise_error -stderr exits with 1
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design -load read
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rename top abc
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delete def
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bugpoint -yosys ../../yosys -command "raise_error -stderr" -expect-return 1
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select -assert-mod-count 1 =*
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select -assert-mod-count 1 other
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#TODO
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# raise_error -stderr prints to stderr
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design -load read
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rename top abc
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delete def
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# bugpoint -yosys ../../yosys -command "raise_error -stderr" -grep "help me"
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# select -assert-mod-count 1 =*
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# select -assert-mod-count 1 other
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