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yosys/passes
Natalia d25171806b wreduce: queue traversal and add regression test
Implement iterative queue-based traversal in wreduce pass to propagate
width reductions across dependent cells and wires. Previously, wreduce
would process all cells once, then all wires once. This meant that
reductions couldn't propagate through chains of operations.

The new algorithm maintains work queues for both cells and wires,
processing them iteratively until no more reductions are possible.
When a cell or wire is reduced, dependent cells and wires are added
back to the queues for reprocessing.

Add regression test to verify that width reductions propagate through
a chain of operations: (a + b)[3:0] + c, ensuring the first addition
is reduced from 9 bits to 4 bits.
2026-01-14 00:32:41 -08:00
..
cmds Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
equiv Merge pull request #5357 from rocallahan/builtin-ff 2025-09-17 11:37:16 +02:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
memory Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
opt wreduce: queue traversal and add regression test 2026-01-14 00:32:41 -08:00
pmgen Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
proc proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
sat Revert sim's cycle_width default back to 10, but keep -width option 2025-10-20 14:40:05 +02:00
techmap Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00