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yosys/techlibs/xilinx
2020-01-06 15:02:44 -08:00
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tests xilinx: Test our DSP48A/DSP48A1 simulation models. 2019-12-23 20:36:43 +01:00
.gitignore
abc9_map.v Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-06 15:02:44 -08:00
abc9_model.v Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-06 15:02:44 -08:00
abc9_unmap.v Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-06 15:02:44 -08:00
abc9_xc7.box Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-06 15:02:44 -08:00
abc9_xc7.lut
abc9_xc7_nowide.lut
arith_map.v
brams_init.py
cells_map.v
cells_sim.v Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-06 15:02:44 -08:00
cells_xtra.py xilinx: Add simulation models for remaining CLB primitives. 2019-12-19 18:04:04 +01:00
cells_xtra.v xilinx: Add simulation models for remaining CLB primitives. 2019-12-19 18:04:04 +01:00
lut_map.v
lutrams.txt
lutrams_map.v
Makefile.inc
mux_map.v
synth_xilinx.cc synth_xilinx -dff to work with abc too 2020-01-02 12:53:26 -08:00
xc3s_mult_map.v
xc3sda_dsp_map.v xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_brams.txt
xc6s_brams_map.v
xc6s_dsp_map.v xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
xc6s_ff_map.v
xc7_brams_map.v
xc7_dsp_map.v
xc7_ff_map.v
xc7_xcu_brams.txt
xcu_brams_map.v
xcu_dsp_map.v
xcup_urams.txt
xcup_urams_map.v
xilinx_dffopt.cc