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106 lines
4.1 KiB
Verilog
106 lines
4.1 KiB
Verilog
// Flipflop intermediate map level
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module \$__FF_NOLSR (input D, C, E, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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generate
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if (_TECHMAP_WIREINIT_Q_ === 1'b1)
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FD1P3JX #(.GSR("DISABLED")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .PD(1'b0), .Q(Q));
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else
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FD1P3IX #(.GSR("DISABLED")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .CD(1'b0), .Q(Q));
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endgenerate
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endmodule
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module \$__FF_SYNCLSR (input D, C, E, R, output Q);
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parameter SR_VAL = 1'b0;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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wire Ci, Ei, Ri, Rg, Dd;
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generate
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if (SR_VAL)
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FD1P3JX #(.GSR("DISABLED")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .PD(R), .Q(Q));
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else
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FD1P3IX #(.GSR("DISABLED")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .CD(R), .Q(Q));
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endgenerate
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endmodule
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module \$__FF_ASYNCLSR (input D, C, E, R, output Q);
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parameter SR_VAL = 1'b0;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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wire _TECHMAP_REMOVEINIT_Q_ = (_TECHMAP_WIREINIT_Q_ === 1'bx || _TECHMAP_WIREINIT_Q_ === SR_VAL);
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wire Ci, Ei, Ri, Rg, Dd;
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generate
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if (SR_VAL)
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FD1P3BX #(.GSR("DISABLED")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .PD(R), .Q(Q));
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else
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FD1P3DX #(.GSR("DISABLED")) _TECHMAP_REPLACE_ (.D(D), .CK(C), .SP(E), .CD(R), .Q(Q));
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endgenerate
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endmodule
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module \$_DFF_P_ (input D, C, output Q); \$__FF_NOLSR _TECHMAP_REPLACE_ (.D(D), .C(C), .E(1'b1), .Q(Q)); endmodule
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module \$_DFFE_PP_ (input D, C, E, output Q); \$__FF_NOLSR _TECHMAP_REPLACE_ (.D(D), .C(C), .E(E), .Q(Q)); endmodule
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module \$_DFF_PP0_ (input D, C, R, output Q); \$__FF_ASYNCLSR #(0) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule
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module \$_DFF_PP1_ (input D, C, R, output Q); \$__FF_ASYNCLSR #(1) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule
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module \$_SDFF_PP0_ (input D, C, R, output Q); \$__FF_SYNCLSR #(0) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule
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module \$_SDFF_PP1_ (input D, C, R, output Q); \$__FF_SYNCLSR #(1) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(1'b1), .Q(Q)); endmodule
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module \$_DFFE_PP0P_ (input D, C, E, R, output Q); \$__FF_ASYNCLSR #(0) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule
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module \$_DFFE_PP1P_ (input D, C, E, R, output Q); \$__FF_ASYNCLSR #(1) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule
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module \$_SDFFE_PP0P_ (input D, C, E, R, output Q); \$__FF_SYNCLSR #(0) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule
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module \$_SDFFE_PP1P_ (input D, C, E, R, output Q); \$__FF_SYNCLSR #(1) _TECHMAP_REPLACE_ (.D(D), .C(C), .R(R), .E(E), .Q(Q)); endmodule
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module \$__NX_TINOUTPAD (input I, OE, output O, inout B);
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BB _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE), .B(B));
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endmodule
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module \$__NX_TOUTPAD (input I, OE, output O);
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OBZ _TECHMAP_REPLACE_ (.I(I), .O(), .T(~OE), .O(O));
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endmodule
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`ifndef NO_LUT
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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if (LUT == 2'b01)
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INV _TECHMAP_REPLACE_ (.A(A[0]), .Z(Y));
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else
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LUT4 #(.INIT($sformatf("0x%04x", {{8{LUT[1]}}, {8{LUT[0]}}}))) _TECHMAP_REPLACE_ (.Z(Y),
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.D(A[0]));
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end else
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if (WIDTH == 2) begin
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localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};
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LUT4 #(.INIT($sformatf("0x%04x", INIT))) _TECHMAP_REPLACE_ (.Z(Y),
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.C(A[0]), .D(A[1]));
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end else
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if (WIDTH == 3) begin
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localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};
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LUT4 #(.INIT($sformatf("0x%04x", INIT))) _TECHMAP_REPLACE_ (.Z(Y),
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.B(A[0]), .C(A[1]), .D(A[2]));
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end else
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if (WIDTH == 4) begin
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LUT4 #(.INIT($sformatf("0x%04x", LUT))) _TECHMAP_REPLACE_ (.Z(Y),
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.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
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end else
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if (WIDTH == 5) begin
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WIDEFN9 #(
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.INIT0($sformatf("0x%04x", LUT[15:0 ])),
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.INIT1($sformatf("0x%04x", LUT[31:16])),
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) _TECHMAP_REPLACE_ (
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.A0(A[0]), .B0(A[1]), .C0(A[2]), .D0(A[3]),
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.A1(A[0]), .B1(A[1]), .C1(A[2]), .D1(A[3]),
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.SEL(A[4]), .Z(Y)
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);
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end
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endgenerate
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endmodule
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`endif
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