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https://github.com/YosysHQ/yosys
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124 lines
3.6 KiB
Bash
Executable file
124 lines
3.6 KiB
Bash
Executable file
#!/bin/bash
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trap 'echo "ERROR in sv_implicit_ports.sh" >&2; exit 1' ERR
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# Simple case
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../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
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module add(input [7:0] a, input [7:0] b, output [7:0] q);
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assign q = a + b;
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endmodule
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module top(input [7:0] a, output [7:0] q);
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wire [7:0] b = 8'd42;
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add add_i(.*);
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endmodule
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EOT
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# Generate block
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../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
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module add(input [7:0] a, input [7:0] b, output [7:0] q);
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assign q = a + b;
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endmodule
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module top(input [7:0] a, output [7:0] q);
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generate
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if (1) begin:ablock
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wire [7:0] b = 8'd42;
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add add_i(.*);
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end
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endgenerate
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endmodule
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EOT
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# Missing wire
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((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
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module add(input [7:0] a, input [7:0] b, output [7:0] q);
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assign q = a + b;
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endmodule
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module top(input [7:0] a, output [7:0] q);
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add add_i(.*);
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endmodule
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EOT
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) 2>&1 | grep -F "ERROR: No matching wire for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
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# Incorrectly sized wire
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((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
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module add(input [7:0] a, input [7:0] b, output [7:0] q);
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assign q = a + b;
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endmodule
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module top(input [7:0] a, output [7:0] q);
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wire [6:0] b = 6'd42;
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add add_i(.*);
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endmodule
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EOT
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) 2>&1 | grep -F "ERROR: Width mismatch between wire (7 bits) and port (8 bits) for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
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# Defaults
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../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
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module add(input [7:0] a = 8'd00, input [7:0] b = 8'd01, output [7:0] q);
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assign q = a + b;
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endmodule
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module top(input [7:0] a, output [7:0] q);
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add add_i(.*);
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endmodule
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EOT
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# Parameterised module
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../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
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module add #(parameter N=3) (input [N-1:0] a = 8'd00, input [N-1:0] b = 8'd01, output [N-1:0] q);
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assign q = a + b;
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endmodule
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module top(input [7:0] a, output [7:0] q);
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add #(.N(8)) add_i(.*);
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endmodule
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EOT
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# Parameterised blackbox module
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../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - <<EOT
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(* blackbox *)
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module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
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endmodule
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module top(input [7:0] a, b, output [7:0] q);
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add #(.N(8)) add_i(.*);
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endmodule
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EOT
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# Parameterised blackbox module - incorrect width
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((../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - || true) <<EOT
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(* blackbox *)
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module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
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endmodule
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module top(input [7:0] a, b, output [7:0] q);
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add #(.N(6)) add_i(.*);
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endmodule
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EOT
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) 2>&1 | grep -F "ERROR: Width mismatch between wire (8 bits) and port (6 bits) for implicit port connection \`q' of cell top.add_i (add)." > /dev/null
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# Mixed implicit and explicit 1
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../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
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module add(input [7:0] a, input [7:0] b, output [7:0] q);
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assign q = a + b;
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endmodule
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module top(input [7:0] a, output [7:0] q);
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add add_i(.b(8'd42), .*);
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endmodule
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EOT
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# Mixed implicit and explicit 2
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(../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
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module add(input [7:0] a, input [7:0] b, output [7:0] q);
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assign q = a + b;
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endmodule
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module top(input [7:0] a, input [9:0] b, output [7:0] q);
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add add_i(.b, .*);
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endmodule
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EOT
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) 2>&1 | grep -F "Warning: Resizing cell port top.add_i.b from 10 bits to 8 bits." > /dev/null
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