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75 lines
1.9 KiB
Verilog
75 lines
1.9 KiB
Verilog
module Example(outA, outB, outC, outD);
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parameter OUTPUT = "FOO";
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output wire [23:0] outA;
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output wire [23:0] outB;
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output reg outC, outD;
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function automatic [23:0] flip;
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input [23:0] inp;
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flip = ~inp;
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endfunction
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generate
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if (flip(OUTPUT) == flip("BAR"))
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assign outA = OUTPUT;
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else
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assign outA = 0;
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case (flip(OUTPUT))
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flip("FOO"): assign outB = OUTPUT;
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flip("BAR"): assign outB = 0;
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flip("BAZ"): assign outB = "HI";
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endcase
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genvar i;
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initial outC = 0;
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for (i = 0; i != flip(flip(OUTPUT[15:8])); i = i + 1)
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if (i + 1 == flip(flip("O")))
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initial outC = 1;
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endgenerate
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integer j;
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initial begin
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outD = 1;
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for (j = 0; j != flip(flip(OUTPUT[15:8])); j = j + 1)
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if (j + 1 == flip(flip("O")))
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outD = 0;
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end
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endmodule
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module top(out);
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wire [23:0] a1, a2, a3, a4;
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wire [23:0] b1, b2, b3, b4;
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wire c1, c2, c3, c4;
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wire d1, d2, d3, d4;
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Example e1(a1, b1, c1, d1);
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Example #("FOO") e2(a2, b2, c2, d2);
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Example #("BAR") e3(a3, b3, c3, d3);
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Example #("BAZ") e4(a4, b4, c4, d4);
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output wire [24 * 8 - 1 + 4 :0] out;
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assign out = {
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a1, a2, a3, a4,
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b1, b2, b3, b4,
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c1, c2, c3, c4,
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d1, d2, d3, d4};
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// `define VERIFY
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`ifdef VERIFY
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assert property (a1 == 0);
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assert property (a2 == 0);
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assert property (a3 == "BAR");
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assert property (a4 == 0);
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assert property (b1 == "FOO");
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assert property (b2 == "FOO");
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assert property (b3 == 0);
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assert property (b4 == "HI");
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assert property (c1 == 1);
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assert property (c2 == 1);
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assert property (c3 == 0);
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assert property (c4 == 0);
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assert property (d1 == 0);
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assert property (d2 == 0);
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assert property (d3 == 1);
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assert property (d4 == 1);
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`endif
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endmodule
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