Robert O'Callahan 8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.		2025-07-22 10:38:38 +00:00
..
check_map.ys
check_map_lut6.ys
map_and.v
map_cmp.v
map_mux.v
map_not.v	gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.	2018-12-05 17:13:27 +00:00
map_or.v
map_xor.v
run-test.sh