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7608985d2c
I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
33 lines
562 B
Systemverilog
33 lines
562 B
Systemverilog
module top(
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output logic [5:0] out
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);
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always_comb begin
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out = '0;
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case ($bits (out)) 6:
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case ($size (out)) 6:
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case ($high (out)) 5:
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case ($low (out)) 0:
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case ($left (out)) 5:
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case ($right(out)) 0:
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case (6) $bits (out):
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case (6) $size (out):
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case (5) $high (out):
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case (0) $low (out):
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case (5) $left (out):
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case (0) $right(out):
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out = '1;
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endcase
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endcase
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endcase
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endcase
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endcase
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endcase
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endcase
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endcase
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endcase
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endcase
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endcase
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endcase
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end
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endmodule
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