yosys/tests/various/attrib05_port_conn.ys at 8be09b5b24ad5f6a09bbc0bc675ac0be241672ca - mirrors/yosys - Libre-Chip.org

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Maciej Kurc b79bd5b3ca Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

2019-06-04 10:42:42 +02:00

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	`# Read and parse Verilog file`
	`read_verilog attrib05_port_conn.v`