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44 lines
1.1 KiB
Text
44 lines
1.1 KiB
Text
read_rtlil << EOF
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autoidx 20
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attribute \src "3510.v:2.1-26.10"
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attribute \cells_not_processed 1
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attribute \tamara_triplicate 1
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module \top
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attribute \src "3510.v:14.3-17.8"
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wire width 4 $0\reg5[3:0]
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attribute $bugpoint 1
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wire width 4 $auto$bugpoint.cc:258:simplify_something$12
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wire $delete_wire$14
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attribute \src "3510.v:13.19-13.59"
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wire width 4 $xnor$3510.v:13$1_Y
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attribute \src "3510.v:11.23-11.27"
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wire width 4 \reg5
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attribute \src "3510.v:8.24-8.29"
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wire width 3 \wire4
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attribute \src "3510.v:3.33-3.34"
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wire width 12 output 1 \y
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attribute \src "3510.v:13.19-13.59"
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cell $xnor $xnor$3510.v:13$1
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parameter \A_SIGNED 0
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parameter \A_WIDTH 3
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parameter \B_SIGNED 0
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parameter \B_WIDTH 4
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parameter \Y_WIDTH 4
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connect \A 3'x
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connect \B $auto$bugpoint.cc:258:simplify_something$12
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connect \Y $xnor$3510.v:13$1_Y
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end
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attribute \src "3510.v:14.3-17.8"
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process $proc$3510.v:14$2
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assign $0\reg5[3:0] { \wire4 [2] \wire4 }
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sync posedge $delete_wire$14
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update \reg5 $0\reg5[3:0]
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end
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connect \y [4:0] { \reg5 1'0 }
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connect \wire4 $xnor$3510.v:13$1_Y [2:0]
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end
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EOF
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prep
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splitcells
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