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yosys/techlibs/xilinx
History
Marcelina Kościelnicka 38a0c30d65 Get rid of dffsr2dff. 
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
2020-04-15 16:22:37 +02:00
..
tests xilinx: Add simulation model for DSP48 (Virtex 4). 2020-01-29 01:40:00 +01:00
.gitignore Added support for initialized xilinx brams 2015-04-06 17:07:10 +02:00
abc9_map.v xilinx: consider DSP48E1.ADREG 2020-03-04 12:04:02 -08:00
abc9_model.v xilinx: consider DSP48E1.ADREG 2020-03-04 12:04:02 -08:00
abc9_unmap.v xilinx: consider DSP48E1.ADREG 2020-03-04 12:04:02 -08:00
arith_map.v xilinx: Initial support for LUT4 devices. 2020-02-07 09:03:22 +01:00
brams_init.py synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
cells_map.v xilinx: Improve flip-flop handling. 2019-12-18 13:43:43 +01:00
cells_sim.v xilinx: consider DSP48E1.ADREG 2020-03-04 12:04:02 -08:00
cells_xtra.py xilinx: Mark IOBUFDS.IOB as external pad 2020-03-20 14:37:38 +01:00
cells_xtra.v xilinx: Mark IOBUFDS.IOB as external pad 2020-03-20 14:37:38 +01:00
lut4_lutrams.txt xilinx: Add support for LUT RAM on LUT4-based devices. 2020-02-07 09:03:22 +01:00
lut6_lutrams.txt xilinx: Add support for LUT RAM on LUT4-based devices. 2020-02-07 09:03:22 +01:00
lut_map.v xilinx: Initial support for LUT4 devices. 2020-02-07 09:03:22 +01:00
lutrams_map.v Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram 2019-12-16 12:06:47 -08:00
Makefile.inc Auto-generate .box/.lut files from specify blocks 2020-02-27 10:17:29 -08:00
mux_map.v Change synth_xilinx's -nomux to -minmuxf <int> 2019-06-24 10:04:01 -07:00
synth_xilinx.cc Get rid of dffsr2dff. 2020-04-15 16:22:37 +02:00
xc2v_brams.txt xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
xc2v_brams_map.v xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
xc3s_mult_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc3sa_brams.txt xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
xc3sda_brams.txt xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
xc3sda_dsp_map.v xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
xc4v_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc5v_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc6s_brams.txt xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
xc6s_brams_map.v xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
xc6s_dsp_map.v xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
xc6s_ff_map.v xilinx: Improve flip-flop handling. 2019-12-18 13:43:43 +01:00
xc7_brams_map.v xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
xc7_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xc7_ff_map.v xilinx: Improve flip-flop handling. 2019-12-18 13:43:43 +01:00
xc7_xcu_brams.txt xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
xcu_brams_map.v xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
xcu_dsp_map.v xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
xcup_urams.txt xilinx: Add URAM288 mapping for xcup 2019-10-23 11:47:44 +01:00
xcup_urams_map.v xilinx: Add URAM288 mapping for xcup 2019-10-23 11:47:44 +01:00
xilinx_dffopt.cc kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00